Rahul Walia

Rahul Walia

PhD Scholar

Department of Electrical Engineering
Indian Institute of Technology Ropar

About Me

I'm a doctoral researcher in the Department of Electrical Engineering at Indian Institute of Technology Ropar (IIT Ropar), working on analog and digital CMOS integrated circuits — including PRBS generators, low-dropout regulators (LDOs), and analog & digital phase-locked loops (PLLs).

I am working under the supervision of Dr. Mahendra Sakare and Dr. Devarshi Das. My doctoral research aims to develop novel focuses on mixed-signal integrated circuit design — building the foundational blocks that clock, power, and test modern silicon systems.

Prior to joining IIT Ropar, I completed my Master's degree in Electrical Engineering from NITTTR Chandigarh and carried out my thesis work at CSIR-CSIO Chandigarh on the topic "A Parallel Real-Time Seismic Event Detector and Classification of Events Using Machine Learning."

Research Interests

VLSI Circuit Design
Analog & Mixed-Signal IC Design
Low-Dropout Regulators (LDOs)
Phase-Locked Loops (PLLs)
PRBS Generators & High-Speed Testing
CMOS Circuit Design & Optimization

Education

Doctor of Philosophy (PhD) in Electrical Engineering

Indian Institute of Technology Ropar

2023 - Present

Research Area: Fractional N Digital Phase Lock Loops (D-PLLs)

Master of Technology (M.Tech) in Electrical Engineering

National Institute of Technical Teachers Training & Research, Chandigarh

2020 - 2022

Thesis: A Parallel Real-Time Seismic Event Detector and Classification of Events Using Machine Learning.

Bachelor of Technology (B.Tech) in Electrical Engineering

Kurukshetra University, Kurukshetra

2013 - 2016

Publications

Journal

R. Rawat et al., “High-performance paper-based DNA-conjugated Ti₃C₂Tₓ bionanoelectrode for rapid point-of-care detection of HPV-16,” IEEE Sensors Journal, vol. 25, no. 9, pp. 15950–15957, May 2025.
DOI: 10.1109/jsen.2025.3551745

Conferences

P. Singh, R. Walia, R. Nagulapalli and M. Sakare, “A Linearity Improved Equalizers for Short-Channel Communication Links,” 35th Irish Signals and Systems Conference (ISSC), Belfast, UK, 2024.
DOI: 10.1109/ISSC61953.2024.10603313

P. Singh, R. Walia, R. Nagulapalli, and M. Sakare, “A Resistorless Active Inductor Based CTLE,” VDAT 2025, Chandigarh, India.

R. Walia, M. Singh, P. Verma, and R. Ghosh, “A parallel signal detector approach for detection of human activities using multiple seismic sensors,” Lecture Notes in Electrical Engineering, pp. 563–576, 2024.
DOI: 10.1007/978-981-99-6855-8_43

Patents

Mahendra Sakare, Puneet Singh, Rahul Walia, and Raja Sekhar Nagulapalli, “An equalizer and method of operation thereof,” Indian Patent Application No. 202311081865, filed Dec 1, 2023.

Mahendra Sakare, Puneet Singh, Rahul Walia, and Raja Sekhar Nagulapalli, “Equalizer and method of operation thereof,” U.S. Patent Application No. 18/615,959, filed Mar 25, 2024.

Mahendra Sakare, Puneet Singh, Rahul Walia, and Rajasekhar Nagulapalli, “A linearity improved equalizers for short-channel communication links,” Indian Patent Application No. 202411043124, filed Jun 3, 2024.

Mahendra Sakare, Rahul Walia, Puneet Singh, and Rajasekhar Nagulapalli, “Method for enhancing power supply rejection ratio in low dropout regulators using a dynamic noise injector,” Indian Patent Application No. 202511021155, filed Mar 8, 2025.

Mahendra Sakare, Puneet Singh, Rahul Walia, Rajasekhar Nagulapalli, and Shonal Chouksey, “Programmable interleaved PRBS generator integrated circuit with uncorrelated outputs,” Indian Patent Application No. 202511024272, filed Mar 18, 2025.

Experience

Teaching Assistant

IIT Ropar

August 2023 - Present

Teaching Experience

Course Code Course Title Role Semester
EE659 Radio Frequency Integrated Circuits Teaching Assistant II Semester of AY 2025-26
EE533 CMOS Analog IC Design Teaching Assistant I Semester of AY 2025-26
EE533 Circuit Simulation Lab Teaching Assistant I Semester of AY 2025-26
EE663 Frequency Synthesizers, Clock and Data Recovery Circuits Teaching Assistant II Semester of AY 2024-25
EE302 Analog Circuits Laboratory Teaching Assistant I Semester of AY 2024-25
GE108 Basic Electronics Teaching Assistant II Semester of AY 2023-24

Research Intern

Research Organization

May 2020 - July 2020

Developed a parallel real-time seismic event detection system with classification of events using machine learning techniques.

Contact

Address

Department of Electrical Engineering
Indian Institute of Technology Ropar
Rupnagar, Punjab - 140001, India

Office

Lab 302
J.C. Bose Block
IIT Ropar